Together, DRAM and NAND represent 96% of the stand-alone memory markets.
DRAM and NAND revenues are expected to grow with 15% and 8% CAGRs between 2020 and 2026 respectively.
.After the substantial oversupply in 2019 – with ASPs down 49% year-over-year for both NAND and DRAM – overall market conditions improved in 2020 thanks to a combination of CAPEX cuts from suppliers and flourishing demand.
The future is looking bright, particularly for DRAM.
Revenues will peak again in 2022, reaching record-high values of$122 billion (DRAM) and $77 billion (NAND).
In the long term, DRAM and NAND revenues are expected to grow to $86 billion (NAND) and $151 billion (DRAM) with CAGR between 2020 and 2926 of about 15% and 8%, respectively.
In the same period, the ASP is expected to decrease by ~5% (DRAM) and ~16% (NAND), driven by cost-per-bit reductions enabled by technology scaling
In 2020 the leading 3D NAND manufacturers have been ramping up the new 1xxL generation and, In parallel, Micron, Samsung and Hynix have been ramping up 1z DRAM technology.
The consolidation of the NAND market has started with the acquisition of Intel’s 3D NAND business by Hynix.
The DRAM oligopoly of Samsung, Hynix , and Micron remained largely unchanged in 2020, with Samsung being the undisputed leader with up to 42% market share.
The Chinese efforts to develop a local Semiconductor memory industry narrowed down to 2 key players: YMTC and CXMT.
The memory-processor interface is key for overcoming bandwidth limitations. CXL and DDR5 will enable the new wave of data-intensive applications.
The new specification brings lower voltage and moves PMICs onto the memory module. It doubles the maximum data rate and increases the die density by a factor of 4 (up to 64Gb). The production of DDR5 memory is now gaining momentum, with all leading DRAM manufacturers having already finalised their mainstream DDR5 designs:
Hynix announced that they are ready to start shipping DDR5 memory to module manufacturers.
Micron have announced sampling of DDR5 memory based on the 1znm technology, targeting RDIMMs for servers.
The DDR5 memory standard will be utilised by Intel’s upcoming server CPUs
Besides DDR, a variety of new open interfaces and protocols are currently in the works: CXL, Gen-Z, OpenCAPI, CCIX.
Among these, CXL is picking up momentum in data centre applications, providing a sweet spot – in terms of capacity and density – for connecting high-capacity DRAM and SCM technologies such as 3D XPoint.