To improve the accuracy of instrumentation systems, digital-to-analog converters have exceeded the 16-bit performance level that previously had to be achieved with bulky, expensive, and slow Kelvin-Varley voltage dividers.
However, over time, as markets and technologies have evolved, the definition of a precision digital-to-analog converter has changed. Advances in semiconductor processing technology, DAC design, and calibration techniques have enabled high linearity digital-to-analog converters. This converter is not only stable and has a short settling time, but also provides 20-bit performance better than 1ppm. These small ICs guarantee performance specifications, require no calibration, and are simple to use.
Applications for 1ppm DACs range from gradient coil control in medical MRI systems to precision source and positioning in mass spectrometry, test and measurement applications.
The circuit shown in Figure 1 provides 1ppm performance, and its key specifications are integral nonlinearity, differential nonlinearity, and 0.1Hz to 10Hz peak-to-peak noise.
In Figure 1, U1 is a 20-bit DAC with a 1ppm linearity specification. U2 is a precision dual amplifier that acts as a drive-sense buffer for the DAC reference input. U3 is a precision output buffer used to drive a load with similar key requirements as a reference buffer, including low noise, low offset voltage, low drift, and low input bias current.
While precision components below 1ppm are available, building a 1ppm system is not an easy task to take lightly. The main error sources in 1ppm accuracy circuits are noise, temperature drift, and thermoelectric voltages.
To achieve a true 1ppm system, noise must be kept to a minimum. The noise spectral density of U1 is 7.5 nV/vHz. The nominal noise density of U2 and U3 is 2.8 nV/vHz, which is well below the noise contribution of the DAC.
Broadband noise can be removed by filtering, but low frequency noise (1/f) in the 0.1Hz to 10Hz range cannot be filtered out. The most effective way to minimize this noise is device optimization and selection. U1 produces 0.6µVp-p noise over a 0.1Hz to 10Hz bandwidth, well below 1LSB (1LSB = 19µV for ±10V outputs). The design target for 1/f noise in the system should be around 0.1LSB or 2µV. The three amplifiers in the signal chain collectively generate approximately 0.2 μVp-p of noise at the output of the circuit. Adding in the 0.6μVp-p noise of U1, the total 1/f noise is expected to be 0.8μVp-p.
Temperature drift is another major source of error in precision circuits. The temperature coefficient of U1 is 0.05ppm/°C. The drift factor of U2 is 0.6µV/°C, which is an overall 0.03ppm/°C drift introduced into the circuit. At the same time, U3 contributes an output drift of 0.03ppm/°C, so that the sum of the three is 0.11 ppm/°C. For regulation and gain circuits, low drift, thermally matched resistor networks such as Vishay’s 300144Z and 300145Z are recommended.
The thermoelectric voltage is the result of the Seebeck effect: a temperature-dependent voltage occurs at the heterometallic junction. The resulting voltage is between 0.2µV/°C (copper-copper junction) to 1mV/°C (copper-copper oxide junction).
The thermoelectric voltage exhibits a low frequency drift similar to 1/f noise. Keeping all connections clean, eliminating oxides, and shielding circuits from airflow can drastically reduce thermoelectric voltages. Figure 4 shows the difference in voltage drift between open and shielded circuits.
long term stability
Precision analog ICs, while stable, do experience long-term aging changes. The long-term stability of the DAC is generally better than 0.1ppm/1000 hours, but the aging is not cumulative and follows the square root rule. If the aging rate of a device is 1ppm/1000 hours, then 2000 hours aging √2ppm, 3000 hours aging √3ppm, and so on. In general, the time increases by a factor of 10 for every 25°C decrease in temperature; therefore, at an operating temperature of 100°C, over a period of 10,000 hours (approximately 60 weeks), the expected aging is 0.1ppm. And so on, over a 10-year period, the expected aging is 0.32ppm.
Circuit Construction and Layout
In circuits where accuracy is a concern, careful consideration of power and ground return layout can help ensure rated performance. When designing a PCB, the analog and digital sections should be separated and confined to different areas of the board.
Sufficiently large (10µF) supply bypass capacitors must be used in parallel with the 0.1µF capacitors on each supply and as close to the package as possible. These capacitors should have low equivalent series resistance and low equivalent series inductance. If a ferrite bead is connected in series on each power supply line, the high frequency noise passing through the device can be further reduced.
The power lines should be run as wide as possible to provide a low impedance path and reduce the effect of glitches on the power lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other components on the board, and should never be near the reference input or under the package. Avoid crossover between digital and analog signals, and their traces on opposite sides of the board should be perpendicular to each other to reduce board feedthrough effects.
Building a 1ppm Analog-to-Digital Conversion Solution
A typical modern 1ppm analog-to-digital conversion solution consists of two 16-bit digital-to-analog converters—a main DAC and an auxiliary DAC. Its output is scaled and combined to produce a higher resolution. The main DAC output is summed with the attenuated auxiliary DAC output, causing the auxiliary DAC to fill the resolution gap between the main DAC LSB steps.
The combined output needs to be monotonic, but linearity does not need to be extremely high because high performance is achieved through constant voltage feedback from a precision analog-to-digital converter that corrects for inherent component errors. Therefore, the circuit accuracy is limited by the ADC and not limited by the DAC. However, due to the requirement for constant voltage feedback and the inevitable loop delay, this solution is slow and the settling time can be several seconds.
Although this circuit can achieve 1ppm accuracy, it is difficult to design, likely to require multiple iterations, and requires a software engine and precision ADC to achieve the target accuracy. In order to guarantee the accuracy of 1ppm, the ADC needs to be calibrated, because there is no ADC that guarantees 1ppm linearity on the market. The block diagram shown here is only a conceptual representation, the real circuit is much more complex, involving multiple gain, attenuation, and summing stages, and including many components.
Digital circuitry is also required to facilitate the interface between the DAC and ADC, not to mention software for error correction.